BRUCE R. CHILDERS [pic], ASSOCIATE PROFESSORDepartment of Computer Science, University of PittsburghFaculty member of the Computer Engineering Program210 S. Bouquet St, Pittsburgh, PA 15260 USAPhone: 412-624-8421 (voice), 412-624-8854 (fax)E-mail: childers "at" cs.pitt.eduOffice: 6409 Sennott Square |
PUBLICATIONS2008Reducing Pressure in Bounded DBT Code Caches International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Atlanta, Georgia , October 2008 Running a Java VM inside an Operating System Kernel: A Networking Case Study ACM International Conference on Virtual Execution Environments (VEE) Seattle, Washington , March 2008 Integrated CPU and Cache Power Management International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'08) Goteborg, Sweden , January 2008 2007Exploring the Interplay of Yield, Area and Performance in Processor Caches IEEE International Conference on Computer Design (ICCD) Lake Tahoe, CA , October 2007 Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Sratchpad International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Salzburg, Austria , October 2007 Limits for a feasible speculative trace reuse implementation International Journal of High Performance Systems Architecture InderScience Publishers, 2007, Vol. 1, No. 1, pp. 69 - 76 Integrated CPU and L2 Cache Voltage Scaling using Machine Learning ACM Conference on Languages, Compilers, and Tools for Embedded Systems San Diego, California , June 2007 Virtual Execution Environments: Support and Tools Workshop on Next Generation Software, International Symposium on Parallel and Distributed Systems Long Beach, California , March 2007 (Invited) Energy Conservation using Power-Aware Cached-DRAM IEEE Transactions on Computers Accepted February 2007 Performance of Graceful Degradation for Cache Faults IEEE International Symposium on VLSI Porto Alegre, Brazil , May 2007 Integrated CPU and L2 Cache Frequency/Voltage Scaling using Supervised Learning HiPEAC Workshop on Statistical and Machine Learning Approaches Applied to Architectures and Compilation (SMART'07) Ghent, Belgium , January 2007 Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems ACM/IEEE International Symposium on Code Generation and Optimization (CGO) San Jose, California , March 2007 2006Power Aware Mapping of Real-Time Tasks to Multiprocessors The Handbook of Parallel Computing: Models, Algorithms, and Applications Edited by Sanguthevar Rajasekaran et al., CRC Press , 2006 A Speculative Trace Reuse Architecture with Reduced Hardware Requirements IEEE Int'l. Symp. on Computer Architecture and High Performance Computing (SBAC-PAD) Oureto, Brazil , October 2006 Catching and Identifying Bugs in Register Allocation 13th International Static Analysis Symposium Seoul, Korea , August 2006 Evaluating Fragment Creation Policies for SDT Systems 2nd Int'l. Conf. on Virtual Execution Environments Ottawa, Canada , June 2006 Profit-driven Scalar Optimization ACM Transactions on Architecture and Compiler Optimization Accepted May 2006, appeared in Vol. 3, Issue 3, pp. 231-262, September 2006 Power Management in External Memory using Power-Aware Cached-DRAM Int'l. Journal on Embedded Systems Accepted January 2006 2005Near-memory Caching for Improved Energy Consumption IEEE Int'l. Conf. on Computer Design (ICCD'05) San Jose, California , October 2005 TDB: A Source-Level Debugger for Dynamically Translated Programs ACM Sixth Int'l. Symp. on Automated and Analysis-Driven Debugging (AADEBUG'05) Monterey, California , September 2005. Planning for Code Buffer Management in Distributed Virtual Execution Environments ACM/USENIX Conference on Virtual Execution Environments (VEE'05) Chicago, Illinois , June 2005 Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM Proceedings of the Schloss Dagstuhl Seminar on Power-Aware Computing Systems book chapter to be published by Springer-Verlag , June 2005. Collaborative Operating System and Compiler Power Management for Real-Time Applications ACM Transactions on Embedded Computing Systems Accepted April 2005. Compile-time planning for overhead reduction in software dynamic translators International Journal on Parallel Programming Vol. 33, No. 2-3, pp. 103-114 , Appeared June 2005 Jazz: A tool for demand-driven structural testing 14th ETAPS Int'l. Conf. on Compiler Construction (CC) Edinburgh, Scotland , April 2005 Demand-driven structural testing with dynamic instrumentation ACM SIGSOFT Int'l. Conf. on Software Engineering (ICSE'05) St. Louis, Missouri , May 2005 A Model-based Framework: An Approach to Profit-Driven Optimization ACM Int'l. Conf. on Code Generation and Optimization (CGO'05) San Jose, California , March 2005 2004Instrumentation in Software Dynamic Translators for Self-Managed Systems ACM SIGSOFT Workshop on Self-Managed Systems during the ACM SIGSOFT 12th Int'l. Symp. on the Foundations of Software Engineering Long Beach, California , October 31-November 1, 2004. Value Predictors for Reuse through Speculation on Traces IEEE 16th Symp. on Computer Architecture and High Performance Computing (SBAC-PAD'04) Foz do Igaucu, Brazil , October 2004, pp. 48-55. An Infrastructure for Designing Custom Embedded Wide Counterflow Pipelines Journal of Microprocessors and Microsystems Accepted July 2004, Volume 29(1), February 2005, pp. 27-40. Compact binaries with code compression in a software dynamic translator Conference on Design, Automation and Test in Europe (DATE'04) Paris, France , February 2004, pp. 1052-1057, Vol. 2. Profile Guided Management of Code Partitions for Embedded Systems Conference on Design, Automation and Test in Europe (DATE'04) Paris, France , February 2004, pp. 1396-1397, Vol. 2. Overhead reduction techniques for software dynamic translation NSF Next Generation Software Workshop, Int'l. Parallel and Distributed Processing Symposium Santa Fe, New Mexico , April 2004 2003SoftTest: A framework for software testing of Java programs Eclipse Technology Exchange Workshop Anaheim, California , October 27, 2003 The Limits of Speculative Trace Reuse on Deeply Pipelined Processors IEEE 15th Symp. on Computer Architecture and High Performance Computing Sao Paulo/SP, Brazil , November 2003, pp. 36-44. Flexible Instrumentation for Software Dynamic Translation Workshop on Exploring the Trace Space for Dynamic Optimization Techniques San Francisco, California , June 2003 Predicting the Impact of Optimizations for Embedded Systems ACM Conference on Languages, Compilers, and Tools for Embedded Systems San Diego, California , June 2003 Energy Management for Real-Time Embedded Applications with Compiler Support ACM Conference on Languages, Compilers, and Tools for Embedded Systems San Diego, California , June 2003 Collaborative Operating System and Compiler Power Management for Real-Time Applications IEEE Real-Time/Embedded Technology and Applications Symposium Washington, DC , May 2003, pp. 133-141 Short Courses in System-on-a-Chip (SoC) Design IEEE Int'l. Conference on Microelectronic Systems Education (MSE) Anaheim, California , June 2003, pp. 126-127 Custom Wide Counterflow Pipelines for High Performance Embedded Applications IEEE Transactions on Computers Accepted January 2003, Vol. 53, No. 2, February 2004, pp. 141-158 IEEE Transactions on Parallel and Distributed Systems Accepted January 2003, appeared July 2003, Vol. 14, No. 7, pp. 686-700 Retargetable and Reconfigurable Software Dynamic Translation ACM SIGMICRO Int'l. Conf. on Code Generation and Optimization San Francisco, California , March 2003, pp. 36-47 Continuous Compilation: A New Approach to Aggressive and Adaptive Code Transformation NSF Next Generation Software Workshop, Int'l. Parallel and Distributed Processing Symposium Nice, France , April 2003 2002Compilers and Operating Systems for Low Power Kluwer Academic Publishers , 2002 200122nd IEEE Real-Time Systems Symposium London, UK , December 2001, pp. 84-94 Toward The Placement of Power Management Points in Real Time Applications Workshop on Compilers and Operating Systems for Low Power October 2001 2000Adapting Processor Supply Voltage to Instruction-Level Parallelism Koolchips Workshop Monterey, California , December 2000 Width-Sensitive Scheduling for Resource Constrained VLIW Processors ACM Workshop on Feedback-Directed and Dynamic Optimization Monterey, California , December 2000 Compiler-Assisted Dynamic Power-Aware Scheduling for Real-Time Applications Workshop on Compilers and Operating Systems for Low Power Philadelphia, Pennsylvania , October 2000 Custom Wide Counterflow Piplines for High-Performance Embedded Applications Int'l. Conference on Parallel Architecture and Compilation Techniques (PACT'00) October 2000, pp. 57-68. Reordering Memory Bus Transactions for Reduced Energy Consumption ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems Vancouver, Canada , June 2000 An Infrastructure for Designing Custom Embedded Counterflow Pipelines Hawaii Int'l. Conf. on System Sciences Maui, Hawaii , January, 2000 1999Automatic Architectural Design of Wide-Issue Counterflow Pipelines Workshop on Compiler and Architecture Support for Embedded Systems (CASES'99) Washington, DC , 1999 Architectural Considerations for Application-Specific Counterflow Pipelines IEEE Conf. on Adv. Research in VLSI (ARVLSI'99) Atlanta, Georgia , March 1999, pp. 3-22 1998A Design Environment for Counterflow Pipeline Synthesis ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'98) Lecture Notes in Computer Science, Springer , June 1998, pp. 223-234, Vol. 1474. 1993Memory Bandwidth Optimizations for Wide-Bus Machines Hawaii Int'l. Conf. on System Sciences January 1993, pp. 466-475, Vol. 1. |
| Updated by childers on Tuesday, August 19, 2008. This page renders best with FireFox. |